As recent rapid trend in modern electronic devices is not only toward lighter and smaller devices, but also toward multi-function and high-performance devices, the integrated-circuit (IC) fabrication and technology has to evolve correspondingly toward a more high-density and miniature design so as to allow more electronic components to be received inside limited chip space. Consequently, the relating IC package structure and the package technology are evolved accordingly to meet the trend.
In the conventional wafer-level or panel-level packaging, a semiconductor die is adhered onto a carrier wafer or a carrier panel by using a removable sticky substance before the molding process of package material. Because of high pressure in the molding process, the semiconductor die may be shifted in position or direction if the adhesion between the semiconductor die and the carrier is not strong enough. Such kind of shift may further cause alignment failures in the formation of the circuitry layer or the redistribution layer (RDL). Therefore, it is in need of a new and advanced packaging solution to reduce the fabrication cost.